DS620U+【PDF 10/15 页】IC THERMOMETER/STAT DIG 8MSOP

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DS620 Digital Thermometer and Thermostat

10 of 15

conversions can be performed.

See Writing the 1SHOT Bit Command Sequence section for writing more

information on writing the 1SHOT bit.

PO2

Read/Write

At power-up, PO2 = 1.

PO2 = 0 forces the PO pin low (see Table 3)

PO2 = 1 configures PO as the thermostat output (PO

-HIGH

or PO

-LOW

, as

determined by PO1).

PO1*

Read/Write

When PO2 = 1, PO1 configures the PO pin as either PO

-HIGH

or PO

-LOW

(see

Table 3)

When PO2 = 0, PO1 is a dont care.

Factory state = 0

Read Only

Shows address bit A

, as determined by pin A2.

Read Only

Shows address bit A

, as determined by pin A1.

Read Only

Shows address bit A

, as determined by pin A0.

Read/Write

User memory for general-purpose data storage.

Stored in EEPROM

Table 6. Resolution Configuration

Resolution

LSb Weight (癈)

Max Conversion

Time (ms)

10-bit

0.5

11-bit

0.25

12-bit

0.125

100

13-bit

0.0625

200

2-WIRE SERIAL DATA BUS

The DS620 communicates over a standard bidirectional 2-wire serial data bus that consists of a serial clock (SCL)

signal and serial data (SDA) signal. The DS620 interfaces to the bus through the SCL input pin and open-drain

SDA I/O pin. All communication is MSb first.

The following terminology is used to describe 2-wire communication:

Master Device: Microprocessor/microcontroller that controls the slave devices on the bus. The master device

generates the SCL signal and START and STOP conditions.

Slave: All devices on the bus other than the master. The DS620 always functions as a slave.

Bus Idle or Not Busy: Both SDA and SCL remain high. SDA is held high by a pullup resistor when the bus is idle,

and SCL must either be forced high by the master (if the SCL output is push-pull) or pulled high by a pullup resistor

(if the SCL output is open-drain).

Transmitter: A device (master or slave) that is sending data on the bus.

Receiver: A device (master or slave) that is receiving data from the bus.

START Condition: Signal generated by the master to indicate the beginning of a data transfer on the bus. The

master generates a START condition by pulling SDA from high to low while SCL is high (see Figure 6). A

repeated START is sometimes used at the end of a data transfer (instead of a STOP) to indicate that the master

will perform another operation.

STOP Condition: Signal generated by the master to indicate the end of a data transfer on the bus. The master

generates a STOP condition by transitioning SDA from low to high while SCL is high (see Figure 6). After the

STOP is issued, the master releases the bus to its idle state.

Acknowledge (ACK): When a device (either master or slave) is acting as a receiver, it must generate an

acknowledge (ACK) on the SDA line after receiving every byte of data. The receiving device performs an ACK by

pulling the SDA line low for an entire SCL period (see Figure 6). During the ACK clock cycle, the transmitting

device must release SDA. A variation on the ACK signal is the not acknowledge (NACK). When the master device

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